There are many applications which use analog-to-digital conversion. Typically, analog signals resulting from an analog process are converted to digital information in order for the artifact of that analog event to be operated upon by a digital computer. There are many such applications which not only require that the results be consistent from one event to the next but also require that the results be accurate to within some predefined limits. One typical system which provides enhanced accuracy for such applications is an algorithmic analog-to-digital converter.
An algorithmic analog-to-digital converter conventionally includes an input sample and hold circuit, an amplifier circuit with a predetermined gain, a comparator to determine the value of the bit currently under consideration, a summing node and a recycling sample and hold circuit for recycling the resulting voltage from the current bit decision in preparation for the next bit decision cycle.
The sample and hold circuits can be any standard sample and hold circuit. The signal sample is coupled to the input of the amplifier circuit for amplification at a predetermined gain. The result from that amplification is then compared to a reference voltage from which one of two actions result.
First, if the result of the amplification is greater than the reference voltage then the most significant bit of the final digital result is set equal to a logical "one". The reference voltage is then subtracted from the result of the amplification. This second result is stored on the recycling sample and hold circuit which can include a gain-of-one op amp. This second result is compared to the reference voltage to determine the next most significant bit in the final digital result.
Second, if the result of the amplification is less than or equal to the reference voltage then the most significant bit is set equal to a logical "zero". The result is passed through the summing node unchanged and coupled to the input of the op amp circuit for the next cycle of the algorithm. The algorithm cycle is continued until all the bits are filled in the final digital result as necessary for the required accuracy.
With the advent of integrated circuit technology and the parallel goals to reduce system size and power consumption, traditional methods for calibrating A/D converters, such as the use of rheostats, are no longer adequate.
Examples of present calibration methods include:
1. Coupling external calibration resistors or capacitors to the integrated circuit; PA1 2. Laser trimming of integrated resistors on the integrated A/D converter circuit; PA1 3. Integrated calibration through fuse link or PROM circuitry on the integrated A/D circuit; and PA1 4. Storing a calibration value in a capacitor which must be refreshed with each A/D conversion cycle such as described in U.S. Pat. Nos. 4,529,965, 4,429,282, 4,543,534, 4,517,549 and 4,555,668.
These methods are inadequate for a variety of reasons. The first method is expensive in that it requires extra components and additional board space. The second and third methods do not allow for any recalibration of the system subsequent to operating shifts due to aging of the circuitry. The fourth method dramatically slows down A/D operation by requiring a calibration cycle during each conversion.
Another technique for improving conversion accuracy involves nulling the offset voltage of the amplifier. During a nulling cycle in prior art op amp circuits the inputs are "zeroed out" by connecting both the inverting and non-inverting inputs to ground through MOS switches. The voltage on the outputs of an op amp with zeroed out inputs, will, have a theoretical value of zero, however, due to D.C. errors and to charge injected to the inputs of the op amp circuit from the gates of each input grounding MOS switch the outputs are often offset from zero. This offset adversely affects the accuracy of the analog-to-digital conversion in proportion to the size of the offset. More details of such a nulling method can be found in the following U.S. Pat. No. 4,417,160.
An improved A/D circuit is needed which is calibratable without external circuitry, without altering the physical structure of the device and which does not lengthen the A/D conversion cycle time.
An improved A/D circuit is needed for which the nulling circuit charge injection and the resulting offset is reduced.